Convert Verilog to Python Assignments

How to Use

1. Enter the array name (e.g., signals or monitored_signals_reg).

2. Paste lines with assignments like assign signals[0] = ABC; or monitored_signals_reg[0] <= OS_REBOOT_N;.

3. Click Convert or wait for auto-update after typing.

4. Indices will be reorganized to 0-X in the order they appear.

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Example:
Array Name: monitored_signals_reg
Verilog Input:

  monitored_signals_reg[0] <= OS_REBOOT_N;
  monitored_signals_reg[2] <= iRebootTrigger; // some comment
  monitored_signals_reg[266] <= delayed_reboot_trigger;

Updated Verilog Output:

  monitored_signals_reg[0] <= OS_REBOOT_N;
  monitored_signals_reg[1] <= iRebootTrigger; // some comment
  monitored_signals_reg[2] <= delayed_reboot_trigger;

Python Output:

  monitored_signals = [
    "OS_REBOOT_N",         # 0
    "iRebootTrigger",      # 1
    "delayed_reboot_trigger", # 2
  ]