Advanced Verilog Port Renaming

How to Use

1. Paste your Verilog lines (or full module code) below.

2. Select a Direction Option to keep, remove, or force a specific port direction.

3. Check Add semicolon if you want a ; appended to each line.

4. Provide any Prefix/Suffix you want to add, and optionally set a Search String and Replace String.

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Example:
- Code:

input wire [7:0] data_in,
output logic valid_out
              

- Direction Option: remove
- Prefix: my_
- Add semicolon: checked

This would transform each line to something like:

my_data_in,
my_valid_out;