Filter Verilog Ports by Direction

How to Use

1. Paste your Verilog snippet in the “Verilog Code” box below.

2. In “Port Declarations to Remove,” list directions to exclude (comma-separated). For example: output, inout.

3. If you want to rename or label the remaining ports, add an optional Prefix or Suffix.

4. Click Filter Ports to see the resulting signals after filtering.

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Example:
Suppose your code has:

input [7:0] data_in;
output data_out;
inout bidir;
              

and you set “Port Declarations to Remove” to output, inout and “Prefix” to my_, you’ll only see:

my_data_in